1. Field of the Invention
This invention relates generally to integrated circuit chips, and more particularly to a system and automated methodology for ac performance tuning of tubbed semiconductor ASIC chips in a timing-safe environment by repairing detected AC defects in the semiconductor die.
2. Description of Related Art
As the performance targets for integrated circuits increase, the presence of AC defects within the manufactured device is of greater concern due to test cost and yield impacts. While present test methodologies test for AC defects, products failing these tests are discarded or sorted into less-profitable speed bins.
In order to improve the AC yield characteristics produced by IC devices, a system and method for tailoring device performance post-manufacture is disclosed. The means described allows for tailoring of the bulk voltage supplied to various well structures within the die, thereby altering the effective threshold voltage and AC performance of the devices present within the well, thus in effect, repairing detected AC defects.
The value of the threshold voltage of a transistor, VT, particularly a MOS transistor, is determined in part by the fabrication process specifications, i.e., the channel length, channel width, doping, and the like. Thus, it is possible to set VT to a desired (predetermined) level during fabrication. It is difficult, however, to choose the VT such that the transistor will operate efficiently over a wide range of supply voltages. Additionally, manufacturing inconsistencies will also cause variations in the threshold voltage among individual transistors.
Several innovative techniques for controlling well bias have been previously disclosed, however, all lack a defined methodology for performing in-situ testing of semiconductors. Moreover, these prior art techniques have not been built around characterized technology circuit delay timing rules, which allow for safe tailoring of threshold voltages via well bias in order to speed up AC performance without introducing new timing problems such as undesired fast paths.
The bulk of today""s semiconductor integrated circuits are designed using Metal-Oxide-Semiconductor-Field-Effect-Transistors (MOSFETs). Although in most designs, MOSFETs are treated as three-terminal devices where the conductivity between the source and the drain of the device is controlled by a gate voltage, MOSFETs are inherently four-terminal devices, in which a fourth terminal, the bulk node, affects the parametric characteristics of the device. The threshold voltage for a MOSFET, VT, is the gate voltage at which conduction between the source and drain begins. This threshold voltage may be tailored by adjusting the bulk voltage, thereby altering the electric field impressed upon the MOSFET during normal operation. Early MOSFET products used p-FETs or n-FETs having differentiation between load and switching devices. These junctions were typically provided by implant tailoring during manufacture. All devices within the die shared a common bulk node with a voltage supplied coincident with the power supplies for the die. In later CMOS devices in which both n-FETs and p-FETs were integrated within the same die, tubs or wells of bulk material were used to house either the n-FET or p-FET. The bulk connections in these devices were generally tied to one of the voltage rails, or alternatively, for devices within a well or tub only, to a node within the operative circuit. Although in many cases, the base wafer upon which the FETs without tubs were produced was highly resistive, the isolation between FET regions was not sufficient for independent back biasing of device regions without wells. In each case, a voltage potential was provided which could not be altered in reference to the supply rails for the die.
In more advanced CMOS technologies, local isolation of both n-FETs and p-FETs within tubs has been achieved by the stacking of tub structures. As an example, n-FET devices fabricated on a p-type wafer may be isolated by first implanting an n-well within the wafer and subsequently creating a p-well within the larger n-well. In these cases, care is taken to bias the intervening tub appropriately to prevent semiconductor latch-up.
In silicon-on-insulator (SOI) technology, n-FETs and p-FETs are both isolated in the locale of device level tubs; however, shallow SOI technologies leave the body of the device floating.
Typical methods for adjusting threshold voltages in semiconductors include disconnecting each bulk region or well from its associated fixed rail voltage and alternatively making a connection to a set of devices acting as a potentiometer to adjust the bias voltage of the bulk region or well, independent of the fixed rail voltages. Each well can be connected to a dedicated potentiometer, or share a potentiometer with other wells on the die. Several embodiments of the bulk bias potentiometer have been realized.
In FIG. 1, the bulk connection 12 is made at the connection point between two series resistors R1, R2 bridging the VCC 5 to VSS 10 envelope. The resistors R1 and R2 are of an arbitrary size which considers power dissipation, accuracy, and predicted optimum bias voltage settings for the circuit, and are trimmable via laser or other types of fuse blow. AC testing is typically performed with nominal biasing of the stack. If a fail occurs, the voltage applied to the stack, VCC 5, is assumed separate from the main VSS supply 10 of the chip, and may be moved higher or lower. The test is repeated to determine a setting at which the AC test produces adequate yields. The empirically determined VCC value 5 is used with either the expected nominal values of the resistors, or the expected ratio of resistor R1 and resistor R2 coupled with an empirical resistor value. This is calculated by measuring the ground current of the stack at a known VCC to determine the bulk bias voltage needed for yield (the bias tap supplies a tub with back biased diodes which generally has very small leakage currents). The calculated voltage is then converted to a trim percentage necessary at either resistor R1 or resistor R2 to obtain the desired bias voltage given the operational VCC value for the silicon. Additional capability can be added by placing shunt devices in parallel with one or more of the resistors in the stack (R1 and R2 may consist of several segments) such that the well may be biased at the VCC rail. This capability also adds additional accuracy to resistor measurements which precede device trim calculations. The trimming accuracy and achievement of the desired AC effect is determined by measurement of VSS current at the specified voltage and by the AC test post trim.
Another method for adjusting threshold voltages in semiconductors is depicted in FIG. 2. This method involves removing the direct connection to VSS for the stack at the chip""s edge 14 in favor of a supply voltage via a bandgap reference system 20. The reference system includes the generation of a VCC 5, a temperature independent reference voltage, and a voltage reference multiplier 18 which may be adjustable. The bandgap itself provides for reference equivalence between the test and functional environments with the voltage multiplier, allowing for biasing of well voltages Vsub above voltages normally possible with a bandgap device. If a voltage multiplication is adjustable, this function takes the place of VCC shifting during test. In cases where variable multiplication is not provided, the VSS reference, being separate from common ground, is assumed to be isolated from other grounds on the die, and can be moved to simulate VCC shifting.
In U.S. Pat. No. 5,917,365 issued to Houston, entitled xe2x80x9cOPTIMIZING THE OPERATING CHARACTERISTICS OF A CMOS INTEGRATED CIRCUIT,xe2x80x9d an n-channel transistor and a p-channel transistor each have a voltage bias applied to a common substrate. A control circuit is operated to apply the varying voltage bias to the common substrate in order to reduce the leakage current in the IC. The control circuit represents a function employed to deliver predetermined bias voltages depending upon two operational modes of the device, active mode and standby mode. However, there is no analytical mechanism for determining the appropriate bias voltage level and then reanalyzing at this new level for system performance during AC testing.
In U.S. Pat. No. 5,397,934 issued to Merrill, et al., entitled xe2x80x9cAPPARATUS AND METHOD FOR ADJUSTING THE THRESHOLD VOLTAGE OF MOS-TRANSISTORS,xe2x80x9d the effective threshold voltage of the MOS-transistor is adjusted by adjusting its source-body voltage potential. The method consists of measuring a first voltage signal, measuring the effective threshold voltage of the MOS-transistor, generating a second voltage signal, comparing the first voltage signal to the second voltage signal, and adjusting the effective threshold voltage of the MOS-transistor so that the second voltage signal is substantially equal to the first voltage signal. The threshold voltage adjusting apparatus, however, is represented solely by hard-wired circuitry with built-in feedback. There are no provisions to analytically determine the appropriate bias voltage threshold levels, recalculate their effectiveness, and then set the levels based on the results of the recalculations.
As indicated by the above-cited prior art, active bulk well voltage control is being used for leakage power control under idle conditions or under program control, in part to enhance product yields, but no methodology or technique currently exists for AC performance tailoring of portions of ASIC devices based on characterized design rule data. Specifically, active circuits are not directly targeted for appropriate and selective threshold voltage shifting.
The advantage of AC performance tailoring is that chips which fail AC tests or speed sorts, devices within the die, and more particularly, subsets of devices within the die, may have their performance incrementally adjusted via bulk bias adjustments in order to meet AC specifications or provide for higher performance sort yields. Ordinarily, such devices would either be scrapped as out-of-specification where performance sorting was not done, or sorted to slower performance sorts with lower profit margins where performance sorting was practiced.
Furthermore, this approach ensures that any modifications made to the hardware are still certified according to the device models via the new design rule data.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to establish a system and methodology for a set of AC performance tests that adjusts test failures through bulk bias voltage variations.
It is another object of the present invention to provide a system and methodology for identifying active circuits during each performance test, isolating failing circuits, and proposing threshold voltages based on this empirical data.
A further object of the invention is to provide a system and methodology for proposing and retesting different bulk well bias voltages on a semiconductor wafer.
Yet another object of the invention is to provide a system and method for tailoring the voltage or voltages applied to bulk nodes, post-manufacture, such that the integrated circuit under test meets its performance target.
It is another object of the present invention to target active IC circuitry for voltage threshold shifting.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method for reducing AC test failures during performance testing of an integrated circuit wafer having a plurality of gates, circuits, and bulk well voltages, the method comprising: analyzing each of the plurality of circuits against a plurality of performance verification test cases; identifying failed circuits that do not pass the plurality of performance verification test cases; calculating voltage threshold values for the failed circuits; performing a static timing analysis on the plurality of circuits, substituting the calculated voltage threshold values for the bulk well voltages; programming the integrated circuit wafer to operate at the calculated voltage threshold values that pass the static timing analysis; and, reanalyzing the plurality of circuits having programmed the calculated voltage threshold values against the plurality of performance verification tests.
This method may further comprise: generating a gate level netlist of the plurality of circuits; and, simulating the netlist on a functional delay simulator against a library of the performance verification test cases and technology circuit delay timing rules. The bulk well voltages are initially preconditioned using nominal bias values.
The nominal bias values are chosen such that there is a trade off between timing performance and power dissipation due to leakage currents. The static timing analysis comprises analyzing the gate level netlist. Calculating the voltage threshold values may further comprise basing the voltage threshold values on the delay timing rules and the static timing analysis. Voltage rails that identify the bulk well voltages required for each of the plurality of gates may be incremented.
The library of performance verification test cases can be predetermined by investigating critical circuit paths from a dynamic timing analysis and a static timing analysis. Each of the performance verification test cases is performed for a separately controlled section of the plurality of circuits. The method may further comprise generating a correlation table of the circuit activity against the performance verification test cases.
In a second aspect, the present invention is directed to a method of adjusting voltage thresholds for reducing AC test failures during integrated circuit wafer testing, the wafer having a plurality of gates, circuits, and bulk well voltages, the method comprising: generating a gate level netlist for the integrated circuit wafer; performing static timing analyses on the gate level netlist; simulating the gate level netlist against performance verification test cases; generating integrated circuit simulation traces for the plurality of circuits; calculating an expected frequency versus process profile; assigning pass/fail timing criteria for each of the performance verification test cases; exercising the performance verification test cases against the plurality of circuits; correlating circuit failures of the performance verification test cases to the plurality of circuits; analyzing and isolating the circuit failures in the integrated circuit wafer based on the pass/fail timing criteria; calculating a list of voltage threshold shifts corresponding to the bulk well voltages; verifying set-up and hold margins of the plurality of circuits using the list of voltage threshold shifts; obtaining voltage threshold corrections; and, applying the voltage threshold corrections to all sites on the integrated circuit wafer.
In a third aspect, the present invention is directed to a processor based system including a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for AC performance tuning by threshold voltage shifting on an integrated circuit wafer having a plurality of gates, circuits, and bulk well voltages, the method steps comprising: analyzing each of the plurality of circuits against a plurality of performance verification test cases; identifying failed circuits that do not pass the plurality of performance verification test cases; calculating voltage threshold values for the failed circuits; performing a static timing analysis on the plurality of circuits, substituting the calculated voltage threshold values for the bulk well voltages; programming the integrated circuit wafer to operate at the calculated voltage threshold values that pass the static timing analysis; and, reanalyzing the plurality of circuits having programmed the calculated voltage threshold values against the plurality of performance verification tests.
The method step of analyzing each of the plurality of circuits further comprises: generating a gate level netlist of the plurality of circuits; and, simulating the netlist on a functional delay simulator against a library of the performance verification test cases and technology circuit delay timing rules.
In a fourth aspect, the present invention is directed to a computer program product comprising: a computer usable medium having computer readable program code means embodied therein for causing AC performance tuning by threshold voltage shifting on an integrated circuit wafer having a plurality of gates, circuits, and bulk well voltages, the computer readable program code means in the computer program product comprising: computer readable program code means for causing a computer to effect analyzing each of the plurality of circuits against a plurality of performance verification test cases; computer readable program code means for causing a computer to effect identifying failed circuits that do not pass the plurality of performance verification test cases; computer readable program code means for causing a computer to effect calculating voltage threshold values for the failed circuits; computer readable program code means for causing a computer to effect performing a static timing analysis on the plurality of circuits, substituting the calculated voltage threshold values for the bulk well voltages; computer readable program code means for causing a computer to effect programming the integrated circuit wafer to operate at the calculated voltage threshold values that pass the static timing analysis; and, computer readable program code means for causing a computer to effect reanalyzing the plurality of circuits having programmed the calculated voltage threshold values against the plurality of performance verification tests.
In a fifth aspect, the present invention is directed to a computer program product comprising: a computer usable medium having computer readable program code means embodied therein for causing AC performance tuning by threshold voltage shifting on an integrated circuit wafer having a plurality of gates, circuits, and bulk well voltages, the computer readable program code means in the computer program product comprising: computer readable program code means for causing a computer to effect generating a gate level netlist for the integrated circuit wafer; computer readable program code means for causing a computer to effect performing static timing analyses on the gate level netlist; computer readable program code means for causing a computer to effect simulating the gate level netlist against performance verification test cases; computer readable program code means for causing a computer to effect generating integrated circuit simulation traces for the plurality of circuits; computer readable program code means for causing a computer to effect calculating an expected frequency versus process profile; computer readable program code means for causing a computer to effect assigning pass/fail timing criteria for each of the performance verification test cases; computer readable program code means for causing a computer to effect exercising the performance verification test cases against the plurality of circuits; computer readable program code means for causing a computer to effect correlating circuit failures of the performance verification test cases to the plurality of circuits; computer readable program code means for causing a computer to effect analyzing and isolating the circuit failures in the integrated circuit wafer based on the pass/fail timing criteria; computer readable program code means for causing a computer to effect calculating a list of voltage threshold shifts corresponding to the bulk well voltages; computer readable program code means for causing a computer to effect verifying set-up and hold margins of the plurality of circuits using the list of voltage threshold shifts; computer readable program code means for causing a computer to effect obtaining voltage threshold corrections; and, computer readable program code means for causing a computer to effect applying the voltage threshold corrections to all sites on the integrated circuit wafer.